Amplifying circuit having bias voltage setting mechanism

ABSTRACT

An amplifying circuit having a bias voltage setting mechanism includes: a first amplifying element that amplifies an input signal and outputs the amplified signal as an output signal; a bias voltage setting unit that generates a bias voltage from the output signal on the basis of a control signal, such as an AGC voltage; and a high impedance element (third resistor) by which the bias voltage is applied to an input portion of the first amplifying element and which, when a component for bias voltage setting, such as a fourth resistor, is externally provided in the bias voltage setting unit, prevents a capacitive component of the component for bias voltage setting from being equivalently connected with respect to the input portion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an amplifying circuit, such as an RFamplifier for a TV tuner, and more particularly, to an amplifyingcircuit having a bias voltage setting mechanism.

2. Description of the Related Art

FIG. 4 is a circuit diagram illustrating an AGC circuit which is anexample of a conventional amplifying circuit.

An AGC circuit 1 shown in FIG. 4 is an amplifying circuit having a gainsetting function, which is provided between an antenna tuning circuit 2and an RF double-tuned circuit 3.

The AGC circuit 1 is a package 1A that is formed by portions surroundedby one-dotted chain line. Within the package 1A, a first amplifyingelement 4, a second amplifying element 5, a first resistor r1, and asecond resistor r2, which are integrally manufactured during a processof manufacturing a semiconductor, are provided.

Each of the first and second amplifying elements 4 and 5 includes atwo-gate type MOSFET. An output from the antenna tuning circuit 2 isinput as an input signal Vin to a first gate terminal g1 of the firstamplifying element 4, and an AGC (automatic gain control) voltage isinput to a second gate terminal g2. The second amplifying element 5 isan FET that controls a bias voltage, and a bias voltage Vb that iscontrolled by the second amplifying element 5 according to a level ofthe AGC voltage is applied to the first gate terminal g1 of the firstamplifying element 4.

The AGC circuit 1 controls an amplification degree according to theintensity of the input signal Vin, that is, a receiving state of anelectric wave signal (intensity of an electric field level).Specifically, the AGC circuit 1 decreases the amplification degree whenthe electric wave signal is strong and increases the electric wavesignal when the electric wave signal is weak.

The AGC circuit 1 is disclosed in JP-A-2001-156565, for example.

The AGC circuit 1 is included in a TV tuner, for example. In this case,it may be required that the bias voltage Vb be changed according to theproduct specifications of a TV tuner. In the AGC circuit 1, the biasvoltage Vb is mainly set by a resistance division ratio of the firstresistor r1 and the second resistor r2 each having a fixed resistance.

Therefore, in order to externally change the bias voltage Vb, theresistance division ratio of the first resistor r1 and the secondresistor r2 needs to be changed. Specifically, it is possible toconsider a first method, in which a third resistor r3 is externallyprovided in parallel to the first resistor r1 outside the package 1Ashown in FIG. 4, for example, between an output terminal of the antennatuning circuit 2 and a ground GND, so as to lower a combined resistancevalue at the first resistor r1 side, and a second method, in which afourth resistor r4 is externally provided in parallel to the secondresistor r2 outside the package 1A shown in FIG. 4, for example, betweenthe antenna tuning circuit 2 and the RF double-tuned circuit 3 so as tolower a combined resistance value at the second resistor r2 side.

However, when the first and second methods are used, following problemsoccur.

In the first method, that is, when the third resistor r3 is externallyprovided in parallel to the first resistor r1, a capacitive component Cdue to the third resistor r3 or an internal circuit pattern is connectedbetween the output of the antenna tuning circuit 2 and the ground in anequivalent manner, as shown in FIG. 4. Here, since the capacitivecomponent C serves to reduce the variation range of a tuning frequencyat the antenna tuning circuit 2, there occurs a problem in that thecapacitive component C has an adverse effect on the antenna tuningcircuit 2.

Further, even in the second method, that is, even when the fourthresistor r4 is externally provided in parallel to the second resistorr2, since a capacitive component due to the fourth resistor r4 serves toreduce the variation range of the tuning frequency, the capacitivecomponent C also has an adverse effect on the antenna tuning circuit 2as described above. Furthermore, since input and output terminals of theAGC circuit 1 are connected through the fourth resistor r4 interposedtherebetween, a feedback circuit is formed between the input and outputterminals of the AGC circuit 1. For this reason, various problems, suchas a variation of a wave form or an abnormal oscillation due to the AGCvoltage variation according to an increase of a feedback capacitance,occur.

SUMMARY OF THE INVENTION

The invention is designed to solve the above problems, and it is anobject of the invention to provide an amplifying circuit having a biasvoltage setting mechanism by which a desired bias voltage correspondingto the product specifications can be easily and externally set and whichdoes not have an adverse effect on a circuit.

According to an aspect of the invention, an amplifying circuit having abias voltage setting mechanism includes: an amplifying element thatamplifies an input signal and outputs the amplified signal as an outputsignal; a bias voltage setting unit that generates a bias voltage fromthe output signal on the basis of a control signal; and a high impedanceelement by which the bias voltage is applied to an input portion of theamplifying element and which, when a component for bias voltage settingis externally provided in the bias voltage setting unit, prevents acapacitive component of the component for bias voltage setting frombeing equivalently connected with respect to the input portion.

In the amplifying circuit having the bias voltage setting mechanismaccording to the invention, since the high impedance element is providedin a feedback path through which a signal is transmitted from an outputside of the amplifying circuit to an input side thereof, it is possibleto prevent effects of the capacitive component, which is generated dueto an electronic component externally provided at the output side of theamplifying circuit, from being transferred to the input side of theamplifying circuit. As a result, it is possible to prevent thecapacitive component from having an adverse effect on an antenna tuningcircuit that is provided at the input side of the amplifying circuit.

Further, in the amplifying circuit having the bias voltage settingmechanism, preferably, the amplifying element, the bias voltage settingunit, and the high impedance element are provided within a package.

In the invention, since the amplifying circuit can be made small, theamplifying circuit can be used for various TV tuners.

Furthermore, in the amplifying circuit having the bias voltage settingmechanism, preferably, the amplifying element is a first FET havingfirst and second gate terminals, and the bias voltage setting unitincludes: a first resistor whose one end is grounded; a second FET whosesource terminal is connected to the other end of the first resistor; anda second resistor connected between a drain terminal of the second FETand an output portion of the amplifying element.

In the invention, it is possible to provide an amplifying circuit thatoperates reliably.

Furthermore, in the amplifying circuit having the bias voltage settingmechanism, preferably, the high impedance element is a third resistorthat is connected between the first gate terminal of the first FET andthe drain terminal of the second FET and has a high resistance.

In the invention, even when various resistors are externally provided atthe output side of the amplifying circuit, it is possible to reliablyprevent the capacitive component due to the resistor from having aneffect on the input side of the amplifying circuit.

In addition, in the amplifying circuit having the bias voltage settingmechanism, preferably, at least a first external terminal connected tothe first gate terminal of the first FET, a second external terminalconnected to a drain terminal of the first FET, a third externalterminal connected to a source terminal of the first FET and the one endof the first resistor, a fourth external terminal connected to thesecond gate terminal of the first FET and a gate terminal of the secondFET, a fifth external terminal connected to the drain terminal of thesecond FET, and a sixth external terminal connected to the sourceterminal of the second FET are provided around a periphery of thepackage.

In the invention, it is possible to easily provide an external resistoraround the periphery of the package having the amplifying circuittherein. As a result, the bias voltage of the amplifying circuit can bereliably set to a voltage value corresponding to the specifications.

In the amplifying circuit having the bias voltage setting mechanism ofthe invention, the bias voltage of the amplifying circuit can bereliably set to a desired voltage value only by providing the externalresistor around the periphery of the package.

In addition, in the amplifying circuit, since the effects due to theexternally-provided resistor can be prevented, it is possible to preventthe variation range of a tuning frequency in an antenna tuning circuit,which is provided at the input side of the amplifying circuit, frombeing reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating an amplifying circuit having abias voltage setting mechanism of the invention;

FIG. 2 is a circuit diagram explaining another operation state of anamplifying circuit having a bias voltage setting mechanism, which issimilar to that shown in FIG. 1;

FIG. 3 is a graph illustrating a characteristic of a gain control ratiowith respect to an AGC voltage in an amplifying device of the invention;and

FIG. 4 is a circuit diagram illustrating an AGC circuit which is anexample of a conventional amplifying circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a circuit diagram illustrating an amplifying circuit having abias voltage setting mechanism of the invention, and FIG. 2 is a circuitdiagram explaining another operation state of an amplifying circuithaving a bias voltage setting mechanism, which is similar to that shownin FIG. 1.

Referring to FIG. 1, an AGC (automatic gain control) circuit, which isan example of an amplifying circuit 10, is provided between an antenna(ANT) tuning circuit 20 and an RF double-tuned circuit 30. For example,the AGC circuit is provided in a TV tuner that conforms to the domesticspecifications or the overseas specifications.

The amplifying circuit 10 is formed as an integrated package 10A on asilicon substrate by means of a semiconductor manufacturing process ofusing a layer forming method, such as a sputtering method or anevaporation method. Within the package 10A, a first amplifying element11, a second amplifying element 12, a first resistor R1, a secondresistor R2, and a third resistor R3 (high impedance element) having ahigh resistance value.

The first amplifying element 11 includes a two-gate type MOSFET havingfirst and second gate terminals g1 a and g1 b, a drain terminal d1, anda source terminal s1. In addition, the second amplifying element 12includes a typical (one-gate type) MOSFET having a gate terminal g2, adrain terminal d2, and a source terminal s2.

Further, first to sixth external terminals 10 a, 10 b, 10 c, 10 d, 10 e,and 10 f are provided around the periphery of the package 10A. Inaddition, each of the terminals of the first and second amplifyingelements 11 and 12 is connected to one of the first to sixth externalterminals 10 a, 10 b, 10 c, 10 d, 10 e, and 10 f provided around theperiphery of the package 10A.

For example, in the first amplifying element 11, the first gate terminalg1 a is connected to the first external terminal 10 a, the drainterminal d1 is connected to the second external terminal 10 b, thesource terminal s1 is connected to the third external terminal 10 f, andthe second gate terminal g1 b is connected to the fourth externalterminal 10 e.

On the other hand, in the second amplifying element 12, the gateterminal g2 is connected to the fourth external terminal 10 e togetherwith the second gate terminal g1 b of the first amplifying element 11,the drain terminal d2 is connected to the fifth external terminal 10 c,and the source terminal s2 is connected to the sixth external terminal10 d.

The first resistor R1 is connected between the source terminal s2 of thesecond amplifying element 12 and the third external terminal 10 f, andthe second resistor R2 is connected between the drain terminal d1 of thefirst amplifying element 11 and the drain terminal d2 of the secondamplifying element 12 (between the second external terminal 10 b and thefifth external terminal 10 c). In addition, the third resistor R3 isconnected between the first gate terminal g1 a of the first amplifyingelement 11 and the drain terminal d2 of the second amplifying element 12(between the first external terminal 10 a and the fifth externalterminal 10 c).

The amplifying circuit 10 constructed as described above is providedbetween the antenna tuning circuit 20 and the RF double-tuned circuit30. That is, an output terminal of the antenna tuning circuit 20 isconnected to the first external terminal 10 a of the amplifying circuit10, and an input terminal of the RF double-tuned circuit 30 is connectedto the second external terminal 10 b. In addition, an input signal Vinoutput from the antenna tuning circuit 20 is input to an input portionof the first amplifying element 11 through the first external terminal10 a, and an output signal Vout that has been amplified is output to theRF double-tuned circuit 30, which is provided at a subsequent stage,through the second external terminal 10 b. In addition, the thirdexternal terminal 10 f is grounded (connected to GND), and an AGCvoltage (control voltage) supplied from outside is applied to the fourthexternal terminal 10 e.

An inductor L and a capacitor C, which are connected in series to eachother, are provided between the drain terminal d1 of the firstamplifying element 11 (second external terminal 10 b) and the groundGND, and a +B voltage which is a predetermined power supply voltage isapplied to a connected portion between the inductor L and the capacitorC.

Hereinafter, an operation of the amplifying circuit 10 will bedescribed.

The AGC voltage is output from a gain control circuit (not shown)provided at the RF double-tuned circuit 30 side and is then input to thesecond gate terminal g1 b of the first amplifying element 11 and thegate terminal g2 of the second amplifying element 12 through the fourthexternal terminal 10 e of the package 10A.

Here, when the AGC voltage is input to the gate terminal g2 of thesecond amplifying element 12, a voltage between the drain terminal d2and the source terminal s2 of the second amplifying element 12 is set toa predetermined drain-source voltage V_(DS) according to the AGCvoltage. Assuming that a drain current flowing through the secondamplifying element 12 is Id1, a voltage Vd2 at the drain terminal d2 canbe set to a value obtained in following equation 1:Vd2=Id1·R1+V _(DS).  [Equation 1]

Further, a voltage Vd2 at the drain terminal d2 of the second amplifyingelement 12 is applied as a bias voltage Vb (=Vd2) to the first gateterminal g1 a of the first amplifying element 11 through the thirdresistor R3. That is, the first resistor R1, the second amplifyingelement 12, and the second resistor R2 serve as a bias voltage settingunit.

The predetermined +B voltage is applied to the drain terminal d1 of thefirst amplifying element 11 through the inductor L. Accordingly, whenthe input signal Vin is input to the first gate terminal g1 a and theAGC voltage is applied to the second gate terminal g1 b, the inputsignal Vin is amplified according to the AGC voltage to be then outputas an output signal Vout to the drain terminal d1 of the firstamplifying element 11.

Next, a case of decreasing the bias voltage Vb according to the productspecifications will be described.

As shown by a dotted line in FIG. 1, in the case of decreasing the biasvoltage Vb, a fourth resistor R4 for bias voltage setting is externallyprovided between the sixth external terminal 10 d and the third externalterminal 10 f which are provided within the package 10A. The fourthresistor R4 is connected in parallel to the first resistor R1.Accordingly, the voltage Vd2 at the drain terminal d2 of the secondamplifying element 12 can be set to a value obtained in followingequation 1:Vd2=Id1·Rx+V _(DS).  [Equation 2]

Here, the Rx is a combined resistor when the first resistor R1 and thefourth resistor R4 are connected in parallel to each other, and the Rxcan be expressed in following equation 3:1/Rx=1/R1+1/R4.  [Equation 3]

Since the first resistor R1 is larger than the combined resistor Rx,that is, R1>Rx, a voltage drop at the combined resistor Rx is smallerthan that at the first resistor R1. For this reason, it is possible tomake the output voltage of the second amplifying element 12, that is,the voltage Vd2 at the drain terminal d2 small. As a result, it ispossible to make the bias voltage Vb (=Vd2), which is applied to thefirst gate terminal g1 a of the first amplifying element 11 through thethird resistor R3, small.

Here, the third resistor R3 has a high resistance value of about severalmegaohms, for example. Accordingly, it is possible to prevent acapacitive component C1 (shown by a dotted line in FIG. 1), which isgenerated due to the externally-provided fourth resistor R4, from beingequivalently connected with respect to an input portion of theamplifying circuit 10 as described above in the related art. In otherwords, it is possible to prevent the capacitive component C1 from beingconnected between the output of the antenna tuning circuit 20 and theground. At this time, the third resistor R3 having the high resistancevalue serves as a high impedance element that prevents effects of acapacitive component, which is generated due to an externally-providedresistor (fourth resistor R4), from being transferred to an input sideof the amplifying circuit 10.

As such, it is possible to prevent the capacitive component C1 fromhaving an adverse effect on the antenna tuning circuit 20. That is, itis possible to prevent the capacitive component C1 from serving toreduce the variation range of a tuning frequency.

Next, a case of increasing the bias voltage Vb according to the productspecifications will be described.

As shown in FIG. 2, in the case of increasing the bias voltage Vb, asixth resistor R6 for bias voltage setting is externally providedbetween the second external terminal 10 b and the first externalterminal 10 c which are provided within the package 10A.

That is, since the sixth resistor R6 is connected in parallel to thesecond resistor R2, a combined resistor Ry between the drain terminal d1of the first amplifying element 11 and the drain terminal d2 of thesecond amplifying element 12 becomes small. For this reason, since atotal resistance value between the drain terminal d1 of the firstamplifying element 11 and the ground GND becomes small, it is possibleto increase the drain current Id1 flowing through the second amplifyingelement 12. Accordingly, since a voltage drop at the first resistor R1becomes large, the voltage Vd2 at the drain terminal d2 of the secondamplifying element 12 can be increased. As a result, it becomes possibleto increase the bias voltage Vb (=Vd2) that is applied to the first gateterminal g1 a of the first amplifying element 11 through the thirdresistor R3.

Even in this case, since the third resistor R3 has a high resistancevalue, it is possible to prevent a capacitive component C2 (shown by adotted line in FIG. 2), which is generated due to theexternally-provided sixth resistor R6, from being equivalently connectedwith respect to the input portion of the amplifying circuit 10 asdescribed above. Accordingly, it is possible to prevent the capacitivecomponent C2 from having an adverse effect on the antenna tuning circuit20. That is, it is possible to prevent the capacitive component C2 fromserving to reduce the variation range of a tuning frequency.

FIG. 3 is a graph illustrating a characteristic of a gain control ratioGR with respect to the AGC voltage in an amplifying device of theinvention. In FIG. 3, a curve A represents a case in which the fifthresistor R5 (for bias voltage setting) is not provided between the fifthexternal terminal 10 c and the sixth external terminal 10 d that areshown in FIGS. 1 and 2, and a curve B represents a case in which thefifth resistor R5 (for bias voltage setting) is provided between thefifth external terminal 10 c and the sixth external terminal 10 d. Inaddition, a curve C represents a case in which a resistor, of which aresistance value is different from that corresponding to the curve B, isused as the fifth resistor R5.

As describe above, in the case in which the fifth resistor R5 for biasvoltage setting is connected between the fifth external terminal 10 cand the sixth external terminal 10 d, it is possible to change thecharacteristic of the gain control ratio GR with respect to the AGCvoltage from the curve A in the case when the fifth resistor R5 is notprovided to the curve B or the curve C. Accordingly, by properlyselecting the fifth resistor R5, the amplifying circuit 10 can have thegain control ratio GR corresponding to the product specifications.

The fifth resistor R5 for bias voltage setting may be solely connected,or may be used in combination with the fourth resistor R4, or may beused in combination with the sixth resistor R6, as necessary. As such,by arbitrarily combining the fourth resistor R4, the fifth resistor R5,and the sixth resistor R6, the gain control ratio GR can have variouscharacteristic curves and it is possible to form the amplifying circuit10 corresponding to various TV tuners that conform to the domesticspecifications or the overseas specifications.

Even in this case, a capacitive component C3, which is generated due tothe due to the externally-provided fifth resistor R5, is connected tothe output terminal of the antenna tuning circuit 20 through the thirdresistor R3 having a high resistance. Accordingly, as describe above, itis possible to prevent the capacitive component C3 of the fifth resistorR5 from being equivalently connected between the output terminal of theantenna tuning circuit 20 and the ground GND. As a result, it ispossible to prevent the capacitive component C3 from having an adverseeffect on the antenna tuning circuit 20. That is, it is possible toprevent the capacitive component C3 from serving to reduce the variationrange of a tuning frequency.

1. An amplifying circuit having a bias voltage setting mechanismcomprising: an amplifying element that amplifies an input signal andoutputs the amplified signal as an output signal; a bias voltage settingunit that generates a bias voltage from the output signal on the basisof a control signal; and a high impedance element by which the biasvoltage is applied to an input portion of the amplifying element andwhich, when a component for bias voltage setting is connected externallyto the bias voltage setting unit, prevents a capacitive component of thecomponent for bias voltage setting from being equivalently connectedwith respect to the input portion.
 2. The amplifying circuit having thebias voltage setting mechanism according to claim 1, wherein theamplifying element, the bias voltage setting unit, and the highimpedance element are provided within a package.
 3. The amplifyingcircuit having the bias voltage setting mechanism according to claim 1,wherein the amplifying element is a first FET comprising two FETs Inwhich a drain terminal of an FET having a first game terminal isconnected to a source terminal of an FET having a second gate terminal,and the bias voltage setting unit includes: a first resistor whose oneend is grounded; a second FET whose source terminal is connected to theother end of the first resistor; and a second resistor connected betweena drain terminal of the second FET and an output portion of theamplifying element.
 4. The amplifying circuit having the bias voltagesetting mechanism according to claim 3, wherein the high impedanceelement is a third resistor that is connected between the first gateterminal of the first FET and the drain terminal of the second FET andhas a high resistance.
 5. The amplifying circuit having the bias voltagesetting mechanism according to claim 3, wherein at least a firstexternal terminal connected to the first gate terminal of the first FET,a second external terminal connected to a drain terminal of the firstFET, a third external terminal connected to a source terminal of thefirst FET and the one end of the first resistor, a fourth externalterminal connected to the second gate terminal of the first FET and agate terminal of the second FET, a fifth external terminal connected tothe drain terminal of the second FET, and a sixth external terminalconnected to the source terminal of the second FET are provided around aperiphery of the package.